1. Field of the Invention
The present invention generally relates to testing of integrated circuits and, more particularly, to full functional testing of integrated circuit chips prior to packaging as part of the process of providing "known good die."
2. Background
Single chip packages are tested and burned-in to detect and remove modules that do not meet design operating characteristics and to detect and remove modules that are likely to fail early in system use. With multi-chip module packages (MCM) having dozens or hundreds of chips, a single chip of marginal functionality or reliability is removed from the module and replaced with another chip, requiring a costly rework process, in order to avoid the loss of the other fully functional chips and the complex and costly multi-chip package structure. Alternatively, chips can be fully tested and burned in before they are mounted in a multi-chip module package to avoid the potential for and the costs associated with MCM rework. In this case the testing and burning in must be accomplished either at wafer level or after the chips have been singulated into individual chips so as to provide chip reliability equal to the reliability desired for the packaged device. Chips meeting these specifications are referred to as a "known good die" (KGD).
The testing of chips before they are singulated from the wafer is made easier by the fact that the wafer is easily held in position and the chips on the wafer are in a regular array. However, testing at the wafer level is not usually adequate to meet the package equivalent functionality specification. Difficulties arise because of the inability to provide a wafer probe able to contact all the die pads at the size and pitch they are found on the chip, the inability of the probe to provide signals at a high enough speed to test the speed of the chip, and the difficulty in providing a wafer tester capable of providing a full program of functional test patterns. In addition, burn-in at the wafer level poses many difficulties, such as the need to contact all chips of a wafer at the elevated temperature used for burn-in. Thus full functional testing of singulated chips either in the absence of or accompanying burn-in is desirable.
The full functional testing and burning-in of chips after dicing has been accomplished by bringing a chip in contact with a substrate, simulating a single chip module package throughout the test and burn-in process. The contact methods have included temporary metallurgical connections of the chip to the substrate, such as the reflow of solder bumps to a substrate; the temporary wirebonding of the die to a substrate; or the use of a clamp mechanism to apply pressure to the chip to make intimate physical contact between the chip interconnection pads and the substrate during test and burn-in. However, this single chip test and burn-in method has been very expensive because of the cost of the substrate and the cost of mounting the chip to the substrate and the cost of dismounting the chip once test and burn-in are complete. Although many substrates are reusable, they are rarely reused to their maximum potential and many more substrates are needed to produce the daily required number of known good dies.
Thus, a structure and method that can lower the cost of testing to provide KGD is very desirable, and such a process is provided by the present invention.